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dual lvcmos / lvttl-to-differential lvhstl translator 85222 datasheet 85222 revision c 5/7/15 1 ?2015 integrated device technology, inc. the 85222 is a dual lvcmos / lvttl-to- differential lvhstl translator. the 85222 has two single ended clock inputs. the single ended clock input accepts lvcmos or lvttl input levels and translates them to lvhstl levels. the small outline 8-pin soic package makes this device ideal for applications where space, high performance and low power are important. for optimum performance, both output pairs need to be terminated, even if one output pair is unused. g eneral description f eatures ? 2 differential lvhstl outputs ? selectable clk0, clk1 lvcmos clock inputs ? clk0 and clk1 can accept the following input levels: lvcmos or lvttl ? maximum output frequency: 350mhz ? part-to-part skew: 350ps (maximum) ? propagation delay: 1.3ns (maximum) ? v oh : 1.2v (maximum) ? 3.3v and 2.5v operating supply ? 0c to 70c ambient operating temperature ? industrial temperature information available upon request ? lead-free package fully rohs compliant b lock d iagram p in a ssignment 85222 8-lead soic 3.90mm x 4.92mm x 1.37mm body package m package top view q0 nq0 q1 nq1 1 2 3 4 q0 nq0 q1 nq1 clk0 clk1 v dd clk0 clk1 gnd 8 7 6 5
dual lvcmos / lvttl-to-differential lvhstl translator 85222 data sheet 2 revision c 5/7/15 t able 1. p in d escriptions t able 2. p in c haracteristics number name type description 1, 2 q0, nq0 output differential output pair. lvhstl interface levels. 3, 4 q1, nq1 output differential output pair. lvhstl interface levels. 5 gnd power power supply ground. 6 clk1 input pulldown lvcmos / lvttl clock input. 7 clk0 input pulldown lvcmos / lvttl clock input. 8v dd power positive supply pin. note: pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. note: unused output pairs must be terminated. refer to application information section for a schematic layout. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k r pulldown input pulldown resistor 51 k
revision c 5/7/15 85222 data sheet 3 dual lvcmos / lvttl-to-differential lvhstl translator t able 3a. p ower s upply dc c haracteristics , v dd = 3.3v5%, v dd = 2.5v5%, t a = 0c to 70c t able 3b. lvcmos / lvttl dc c haracteristics , v dd = 3.3v5%, v dd = 2.5v5%, t a = 0c to 70c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v v dd positive supply voltage 2.375 2.5 2.625 v i dd power supply current 45 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage clk0, clk1 2 v dd + 0.3 v v il input low voltage clk0, clk1 -0.3 1.3 v i ih input high current clk0, clk1 v dd = v in = 3.465v, v dd = v in = 2.625v 150 a i il input low current clk0, clk1 v dd = v in = 3.465v, v dd = v in = 2.625v -5 a t able 3c. lvhstl dc c haracteristics , v dd = 3.3v5%, v dd = 2.5v5%, t a = 0c to 70c symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 1 1.2 v v ol output low voltage; note 1 v dd = 3.3v 5% . v v dd = 2.5v 5% .55 v v v v dd = 3.3v 5% . .2 v v dd = 2.5v 5% .5 .2 v 5 d. v v dd .v v .5v v dd .5v 5 2. 5 5 . . dc characteristics or ac charac- teristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
dual lvcmos / lvttl-to-differential lvhstl translator 85222 data sheet 4 revision c 5/7/15 t able 4a. ac c haracteristics , v dd = 3.3v5%, t a = 0c to 70c symbol parameter test conditions minimum typical maximum units f max output frequency 350 mhz t pd propagation delay; note 1 ? 350mhz 750 950 1150 ps tsk(pp) part-to-part skew; note 2, 3 350 ps t r output rise time 20% to 80% 150 800 ps t f output fall time 20% to 80% 150 800 ps odc output duty cycle ? 150mhz 48 52 % 150 < ? 250mhz 47 53 % 250 < ? 350mhz 45 55 % note 1: measured from v dd /2 of the input to the differential output crossing point. note 2: de ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. note 3: this parameter is de ned in accordance with jedec standard 65. t able 4b. ac c haracteristics , v dd = 2.5v5%, t a = 0c to 70c symbol parameter test conditions minimum typical maximum units f max output frequency 350 mhz t pd propagation delay; note 1 ? 350mhz 850 1075 1300 ps tsk(pp) part-to-part skew; note 2, 3 450 ps t r output rise time 20% to 80% 150 800 ps t f output fall time 20% to 80% 150 800 ps odc output duty cycle ? 150mhz 45 55 % 150 < ? 350mhz 40 60 % note 1: measured from v dd /2 of the input to the differential output crossing point. note 2: de ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. note 3: this parameter is de ned in accordance with jedec standard 65.
revision c 5/7/15 85222 data sheet 5 dual lvcmos / lvttl-to-differential lvhstl translator p arameter m easurement i nformation 2.5v c ore /2.5v o utput l oad ac t est c ircuit p ropagation d elay o utput r ise /f all t ime 3.3v c ore /3.3v o utput l oad ac t est c ircuit o utput d uty c ycle /p ulse w idth /p eriod p art - to -p art s kew
dual lvcmos / lvttl-to-differential lvhstl translator 85222 data sheet 6 revision c 5/7/15 a pplication i nformation s chematic e xample figure 1 shows a schematic example of 85222. in this example, the inputs are driven by 7 output lvcmos drivers with series terminations. the decoupling capacitors should be physically f igure 1. 85222 lvhstl b uffer s chematic e xample r5 43 zo = 50 ohm r2 50 ro ~ 7 ohm q1 driver_lvcmos vdd=3.3v r4 50 zo = 50 ohm vdd=3.3v ro ~ 7 ohm q2 driver_lvcmos r1 50 u1 ics85222 1 2 3 4 8 7 6 5 q0 nq0 q1 nq1 vdd clk0 clk1 gnd zo = 50 ohm lvhstl input + - c1 0.1u r6 43 r3 50 zo = 50 ohm zo = 50 ohm lvhstl input + - vdd=3.3v zo = 50 ohm located near the power pin. for 85222, the unused output need to be terminated.
revision c 5/7/15 85222 data sheet 7 dual lvcmos / lvttl-to-differential lvhstl translator p ower c onsiderations this section provides information on power dissipation and junction temperature for the 85222. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 85222 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 3.465v * 45ma = 155.9mw ? power (outputs) max = 78.9mw/loaded output pair if all outputs are loaded, the total power is 2 * 78.9mw = 157.8mw total power _max (3.465v, with all outputs switching) = 155.9mw + 157.8mw = 313.7mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for the devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3c/w per table 5 below . therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.314w * 103.3c/w = 102.4c. this is well below the limit of 125c this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air ow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 5. t hermal r esistance ja for 8-p in soic, f orced c onvection
dual lvcmos / lvttl-to-differential lvhstl translator 85222 data sheet 8 revision c 5/7/15 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvhstl output driver circuit and termination are shown in figure 2. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load. pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = (v oh_max /r l ) * (v dd_max - v oh_max ) pd_l = (v ol_max /r l ) * (v dd_max - v ol_max ) pd_h = (1.2v/50 ) * (3.465v - 1.2v) = 54.4mw pd_l = (0.4v/50 ) * (3.465v - 0.4v) = 24.52mw total power dissipation per output pair = pd_h + pd_l = 78.9mw f igure 2. lvhstl d river c ircuit and t ermination
revision c 5/7/15 85222 data sheet 9 dual lvcmos / lvttl-to-differential lvhstl translator r eliability i nformation t ransistor c ount the transistor count for 85222 is: 443 t able 6. ja vs . a ir f low t able for 8 l ead soic ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
dual lvcmos / lvttl-to-differential lvhstl translator 85222 data sheet 10 revision c 5/7/15 p ackage o utline - m s uffix for 8 l ead soic t able 7. p ackage d imensions reference document: jedec publication 95, ms-012 symbol millimeters minimum maximum n8 a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 basic h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 0 8
revision c 5/7/15 85222 data sheet 11 dual lvcmos / lvttl-to-differential lvhstl translator t able 8. o rdering i nformation part/order number marking package shipping packaging temperature 85222amlf 85222aml 8 lead ?lead-free? soic tube 0c to 70c 85222AMLFT 85222aml 8 lead ?lead-free? soic tape & reel 0c to 70c note: parts that are ordered with an ?lf? suf x to the part number are the pb-free con guration and are rohs compliant.
dual lvcmos / lvttl-to-differential lvhstl translator 85222 data sheet 12 revision c 5/7/15 revision history sheet rev table page description of change date b t2 t8 1 2 12 features section - add lead-free bullet. pin characteristics table - changed c in 4pf max. to 4pf typical. ordering information table - added lead-free part number. updated data sheet format. 3/31/05 bt8 11 13 updated datasheet?s header/footer with idt from ics. removed ics pre x from part/order number column. added contact page. 8/5/10 c t8 11 ordering information - removed leaded devices. updated datasheet format 12/19/14 c1 product discontinuation notice - pdn cq-15-03 5/7/15
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